Conventionally, a semiconductor device in which a logic circuit is arranged in accordance with a specification of a target system is formed on a periphery of a large-scale macro cell (i.e., a CPU and a memory cell), which is formed as a core of the semiconductor device on a single substrate. In such a semiconductor device, in general, power supply wiring lines for the entire semiconductor device are arranged such that metal wiring lines in upper layers are formed in a matrix. Further, a power supply wiring layer for the macro cell is provided as power supply straps above the macro cell. The power supply wiring layer for the macro cell is connected to the power supply wiring lines for the entire semiconductor device through vias, and thus electric power is supplied to the macro cell.
The vias are typically arranged to fill the layers of the entire power supply wiring lines for the macro cell region. Other wiring lines, such as signal lines, in the semiconductor device, therefore, cannot pass through the region where the macro cell is disposed. For example, in a case where the macro cell is provided between nodes to be connected to each other with a signal wiring line, the signal wiring line needs to extend from one of the nodes toward the other node along a path around the macro cell. As a result, congestion of signal wiring lines that need to detour occurs in a portion around the macro cell in the semiconductor device. The congestion of signal wiring lines around the macro cell adversely affects the semiconductor device in such a way that the congestion prevents reduction in the area of the semiconductor device and reduction in the number of wiring layers. As a result, the area of the semiconductor device and the number of layers therein cannot be reduced.
For example, in a case where the macro cell is a memory cell, the degree of the congestion of signal wiring lines around the macro cell further increases. That is, the memory cell typically comprises a memory cell array and a controller, which controls input/output operation between the memory cell and an external device, and thus the controller is typically disposed in the memory cell and adjacent to the external device. Further, since the controller consumes the most power in the memory cell, power supply wiring layers for the memory cell are disposed above the controller to achieve maximum efficiency. The power supply wiring layers for the memory cell are, therefore, typically disposed in the memory cell and adjacent to the external device so that the power supply wiring layers undesirably tend to physically interfere with signal wiring lines in the vicinity of the memory cell. Therefore, the degree of congestion of the signal wiring lines around the memory cell further increases.
Japanese Patent Publication No. 2001-160613 (hereinafter the “'613 publication”) discloses a semiconductor device that includes a macro cell region and a logic region formed around the macro cell region and in which the macro cell region has a logic wiring region for providing wiring lines in the logic region. More specifically, the semiconductor device disclosed in the '613 publication, which is configured so that the macro cell region includes the wiring region in the logic region, allows the wiring lines in the logic region to be provided in the macro cell region, whereby the semiconductor device reduces the necessity of routing the wiring lines in the logic region around the macro cell region. Consequently, the semiconductor device disclosed in the '613 publication achieves reduction in the capacitance of the wiring lines in the logic region and prevention of congestion of the wiring lines around the macro cell region, and thereby the semiconductor device achieves high speed operation of a circuit and a high density of integration of the circuit.
Japanese Patent Publication No. 2010-123895 (hereinafter the “'895 publication”) discloses a semiconductor device and a design method that allow the use of cells in which vias are disposed in the vicinity of power supply wiring lines. More specifically, the semiconductor device disclosed in the '895 publication in which power supply straps in an upper-level metal wiring layer are disposed at fixed intervals on a chip surface that comprises cell power supply wiring lines in a low-level wiring layer disposed in the direction perpendicular to the power supply straps and an intermediate metal wiring layer connected to the power supply straps and disposed in parallel to the cell power supply wiring lines, wherein a plurality of power supply vias that connect the intermediate metal wiring layer and the cell power supply wiring lines to each other are grouped and disposed in high-density regions, low-density regions, and no-via regions in which area-saving cells are disposed. The area-saving cells are cells in which cell areas are reduced by disposing in-cell vias in the vicinity of the power supply wiring lines. Thus, the semiconductor device and layout method disclosed in the '895 publication allow the use of cells in which vias are disposed in the vicinity of the power supply wiring lines, thereby achieving area saving of cells.
In the semiconductor device disclosed in the '613 publication described above, the congestion of the signal wiring lines around the macro cell region can be reduced in a manner that the macro cell region has the logic wiring region for providing signal wiring lines in the logic region. However, the '613 publication does not disclose how to provide the logic wiring region in the macro cell region. The semiconductor device disclosed in the '613 publication decreases the current and power supply voltage supplied to the macro cell region due to a large logic wiring region provided in the macro cell region and inefficiently utilizes the unused regions in the macro cell region due to a small logic wiring region provided in the macro cell region. Further, the '613 publication, which requires modification of the macro cell region itself, increases the number of man-hours required to design the semiconductor device due to the modification of the macro cell region.
In the method for designing a semiconductor device disclosed in the '895 publication described above, by way of adjusting the density of the vias along the power supply wiring lines and arranging regions where no vias are disposed along the power supply wiring lines, regions which allow use of cells in which vias are disposed in the vicinity of the power supply wiring lines are formed to save space in the cells. However, the design method cannot reduce the congestion of signal wiring lines around the macro cell region. Further, the '895 publication, which requires modification of the cells, also increases the number of man-hours required to design the semiconductor device due to the modification of the cells, as in the '613 publication.
One or more embodiments of the present invention provide a semiconductor device design method that efficiently solves congestion of signal wiring lines and, thus, allows reduction in the chip area of and reduction in the number of wiring layers in the semiconductor device.
More specifically, one or more embodiments of the present invention provide a semiconductor device design method that solves congestion of signal wiring lines that occurs around a macro cell region by efficiently arranging vias in the macro cell and, thus, allows reduction in the chip area of and reduction in the number of wiring layers in the semiconductor device.